Design basis of combinational logic circuit 組合邏輯電路設計基礎
Combinational logic circuit 組合邏輯電路
Finally , we study two applications of bdd . the first one is the fault detect of combinational logic circuits 最后,研究了基于bdd的組合電路的故障檢測方法和基于bdd的網絡可靠度的計算方法等兩方面的應用。
The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance 仿真實驗結果證明了改進演化算法對于實現函數級數字組合邏輯電路的硬件演化是可行的,并且提高了演化算法的演化效率和收斂性能。
Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of classicepglo chip of altera co . and the detailed analyses of typical examples are also given 結合altera公司classicep610芯片的結構,研究了將演化算法應用于函數級數字組合邏輯電路的硬件演化,并且對典型實例進行了詳細分析。